MIC74
2-Wire Serial I/O Expander
and Fan Controller
General Description
The MIC74 is a fully programmable serial-to-parallel I/O
expander compatible with the SMBus™ (system manage-
ment bus) protocol. It acts as a “slave” on the bus,
providing eight independent I/O lines.
Each I/O bit can be individually programmed as an input or
output. If programmed as an output; each I/O bit can be
programmed as an open-drain or complementary push-pull
output. If desired, the four most significant I/O bits can be
programmed to implement fan speed control. An internal
clock generator and state machine eliminate the overhead
generally associated with “bit-banging” fan speed control.
Programming the device and reading/writing the I/O bits is
accomplished using seven internal registers. All registers
can be read by the host. Output bits are capable of directly
driving high-current loads such as LEDs. A separate
interrupt output can notify the host of state changes on the
input bits without requiring the MIC74 to perform a
transaction on the serial bus or be polled by the host.
Three address selection inputs are provided, allowing up
to eight devices to share the same bus and provide a total
of 64 bits of I/O.
The MIC74 is available in an ultra-small-footprint 16-pin
QSOP. Low quiescent current, small footprint, and low
package height make the MIC74 ideal for portable and
desktop applications.
Data sheets and support documentation can be found on
Micrel’s web site at www.micrel.com.
Features
•
Provides eight bits of general purpose I/O
•
Built in fan speed control logic (optional)
•
2-wire SMBus™/I
2
C™ compatible serial interface plus
interrupt output
•
2.7V to 3.6V operating voltage range
•
5V-tolerant I/O
•
Low quiescent current: 2µA (typical)
•
Bit-programmable I/O options:
– input or output
– push-pull or open-drain output
– interrupt on input changes
•
Outputs can directly drive LEDs (10mA I
OL
)
•
Up to 8 devices per bus
Applications
•
•
•
•
•
General purpose I/O expansion via serial bus
Personal computer system management
Distributed sensing and control
Microcontroller I/O expansion
Fan Control
Ordering Information
Part Number
Standard
MIC74BQS
Pb-Free
MIC74YQS
Temperature
Range
–40° to +85°C
Package
16-Pin QSOP
Typical Application
3.0V
MIC74
R9
ALERT
DATA
CLK
VDD
/ALERT
DATA
CLK
A0
A1
A2
GND
P0
P1
P2
P3
P4
P5
P6
P7
LED1
3.0V
R1
R2
R3
R4
R5
R6
R7
R8
LED8
Serial-Bus-Controlled LED Annunciator
SMBus is a trademark of Intel Corporation. I C is a trademark of Phillips Electronics N.V.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
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Micrel, Inc.
MIC74
Pin Configuration
A0 1
A1 2
A2 3
P0 4
P1 5
P2 6
P3 7
GND 8
16-Pin QSOP (QS)
16 VDD
15 DATA
14 CLK
13 /ALERT
12 P7 (/FS2)
11 P6 (/FS1)
10 P5 (/FS0)
9 P4 (/SHDN0)
Pin Description
Pin Number
1–3
4–7
8
9 – 12
Pin Name
A0 – A2
P0 – P3
GND
P4 – P7
(/SHDN, /FS0 – FS2)
Pin Function
Address (Input): Slave address selection inputs; sets the three least significant bits of the
MIC74’s slave address.
Parallel I/O (Input/Output): General-purpose I/O pin. Direction and output type are user
programmable.
Ground
Parallel I/O (Input/output): P4–P7 are general-purpose I/O pins. Direction and output type
are user programmable.
Shutdown (Output): When the FAN bit is set, pin 9 becomes SHDN.
Fan Speed (Output): When the FAN bit is set, pins 10 through 12 become /FS0–/FS2
respectively, controlled by the FAN_SPEED register.
Interrupt (Output): Active-low, open-drain output signals input-change-interrupts to the host
on this pin. Signal is cleared when the bus master (host) polls the ARA (alert response
address = 0001 100) or reads status.
Serial Bus Clock (Input): The host provides the serial bit clock in this input.
Serial Data (Input/Output): Serial data input and open-drain serial data output.
Power Supply (Input).
13
/ALERT
14
15
16
CLK
DATA
VDD
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MIC74
Absolute Maximum Ratings
(1)
Supply Voltage (V
DD
)...................................................+4.6V
Input Voltage
[all pins except
V
DD
and GND]
(V
IN
)........................ GND – 0.3V to 5.5V
Junction Temperature (T
J
) ....................................... +150°C
Lead Temperature (soldering, 10 sec.).................... +260°C
EDS Rating
(3)
V
DD
........................................................................ 1.5kV
A0, A1, A2..............................................................500V
Others ....................................................................200V
Operating Ratings
(2)
Supply Voltage (V
DD
).................................... +2.7V to +3.6V
Ambient Temperature (T
A
) .......................... –40°C to +85°C
Package Thermal Resistance ................................163°C/W
Electrical Characteristics
2.7V
≤
V
DD
≤
3.6V; T
A
= 25°C,
bold
values indicate –40°C < T
A
< +85°C, unless noted.
Symbol
V
IN
I
DD
I
START
Parameter
Input Voltage, any pin except
V
DD
and GND
Operating Supply Current
Fan Startup Supply Current
(Fan Mode Only)
P[7:0] inputs; P[7:0] = V
DD
or GND
/ALERT open; f
CLK
= 100kHz
during t
START
; /ALERT, /SHDN,
/FS2[2:0] = open;
V
SMBCLK
= V
SMBDATA
= V
DD
;
P[3:0] = inputs
/ALERT = open,
V
SMBCLK
= V
SMBDATA
= V
DD
;
P[3:0] = inputs
–0.3
2
I
OL
= 3mA
V
IN
= 5.5V or GND
–1
10
–0.5
2
V
OL
= 0.4V, V
DD
= 2.7V
V
OL
= 1V, V
DD
= 3.3V
I
OH
I
LEAK
C
IN
C
OUT
V
IL
V
IH
I
LEAK
/ALERT
V
OL
I
LEAK
Output Low Voltage
Leakage Current
I
OL
= 1mA
V
IN
= V
DD
or V
SS
–1
±250
0.4
+1
V
µA
Output High Current
Leakage Current
Input Capacitance
Output Capacitance
Input Low Voltage
Input High Voltage
Leakage Current
V
IN
= V
DD
or GND
–0.3
0.7V
DD
–250
V
OH
= 2.4V
V
IN
= 5.5V or GND
7
10
7
–1
10
10
0.3V
DD
V
DD
+0.3
+250
+1
0.8
5.5
1
Condition
Min
GND–0.3
2
Typ
Max
5.5
6
1.75
Units
V
µA
mA
I
STBY
Standby Supply Current
3
µA
Serial I/O (DATA, CLK)
V
IL
V
IH
V
OL
I
LEAK
C
IN
V
IL
V
IH
I
OL
Input Low Voltage
Input High Voltage
Output Low Voltage
Leakage Current
Input Capacitance
Input Low Voltage
Input High Voltage
Output Low Current
0.8
5.5
0.4
+1
V
V
V
µA
pF
V
V
mA
mA
mA
µA
pF
pF
V
V
nA
Parallel I/O [P0–P3, P4(/SHDN), P5(/FS0)–P7(/FS2)]
Address Input (A0–A2)
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Symbol
t
START
t
PULSE
t
/INT
t
/IR
t
HD:STA
Parameter
Fan Startup Interval
Minimum Pulse-Width
Interrupt Delay
Delay from Status Read or ARA
Response to /ALERT
≥
V
OH
Hold Time,
Note 7
hold time after repeated start condition,
after this period, the first clock is
generated
repeated start condition setup time
Note 7
Note 7
Note 7
Note 4, 7
Note 5, 7
Note 5, 7
Note 6, 7
Note 6, 7
Note 7
4.7
4
Condition
normal operation
minimum pulse-width on Pn to generate
an interrupt,
Note 7
interrupt delay from state change on Pn to
/ALERT
≤
V
OL
,
Note 7
Min
0.5
10
4
4
Typ
1
Max
3.3
MIC74
Units
sec
ns
µs
µs
µs
AC Characteristics
t
SU:STA
t
SU:STO
t
HD:DAT
t
SU:DAT
t
TIMEOUT
t
LOW
t
HIGH
t
F
t
R
t
BUF
Notes:
Setup Time,
Note 7
Stop Condition Setup Time
Data Hold Time
Data Setup Time
Clock Low Time-Out
Clock Low Period
Clock High Period
Clock/Data Fall Time
Clock/Data Rise Time
Bus free time between stop and
Start condition
4.7
4
500
0
25
4.7
4
50
300
1000
35
µs
µs
ns
ns
ms
µs
µs
ns
ns
µs
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating.
3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF.
4. Devices participating in a transfer will timeout when any clock low exceeds the value of t
TIMEOUT(min)
of 25ms. Devices that have detected a timeout
condition must reset the communication no later than t
TIMEOUT(max)
of 35ms. The maximum value specified must be adhered to by both a master and a
slave as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).
5. t
HIGH(max)
provides a simple guaranteed method for devices to detect bus idle conditions.
6. Rise and fall time is defined as follows: t
R
= V
IL(max)
– 0.15V to V
IH(min)
+ 0.15V; t
F
= 0.9V
DD
to V
IL(max)
– 0.15V.
7. Guaranteed by design.
Timing Definitions
t
R
CLK
t
LOW
t
HD:STA
t
BUF
DATA
StoP
Start
Start
StoP
t
HD:DAT
t
SU:DAT
t
HD:STA
t
HIGH
t
SU:STA
t
SU:STO
t
F
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MIC74
Register Descriptions
Device Configuration Register
DEV_CFG
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
FAN
D[0]
IE
D[7]
OUT7
D[6]
OUT6
D[5]
OUT5
Always write as zero
Output Configuration Register
OUT_CFG
D[4]
OUT4
D[3]
OUT3
D[2]
OUT2
D[1]
OUT1
D[0]
OUT0
Power-On Default Value: 0000 0000
b
, 00
h
Interrupts disabled
Not in Fan Mode
Command_byte addess: 0000 0000
b
, 00
h
Type:
8-bits, read/write
Bit Name: IE
Function: Global interrupt enable
Operation: 1 = enabled
0 = disabled
Bit Name:
Function:
FAN
Selects Fan Mode
(P[7:4] vs. /FS[2:0], /SHDN)
Operation: 1 = Fan Mode
0 = I/O Mode
Bit Name: D[2] through D[6]
Function: Reserved
Operation: Reserved—always write as zero
Data Direction Register
DIR
D[7]
DIR7
D[6]
DIR6
D[5]
DIR5
D[4]
DIR4
D[3]
DIR3
D[2]
DIR2
D[1]
DIR1
D[0]
DIR0
Power-On Default Value: 0000 0000
b
, 00
h
all outputs open-drain
Command_byte addess: 0000 0010
b
, 02
h
Type:
8-bits, read/write
OUTn
Selects output driver configuration of Pn when
Pn is configured as an output.
Operation: 1 = push-pull
0 = open-drain
Notes:
If Fan Mode is selected, that is, the FAN bit of
the DEV_CFG register is set to one, P[7:4] are
automatically configured as open-drain out-
puts. They are then referred to as /FS[2:0] and
/SHDN. The OUT_CFG register has no effect
on these I/O bits while in Fan Mode.
Bit Name:
Function:
Status Register
STATUS
D[7]
S7
D[6]
S6
D[5]
S5
D[4]
S4
D[3]
S3
D[2]
S2
D[1]
S1
D[0]
S0
Power-On Default Value: 0000 0000
b
, 00
h
all Pn’s configured as inputs
Command_byte addess: 0000 0001
b
, 01
h
Type:
8-bits, read/write
Bit Name: DIRn
Function: Selects data direction, input or output, of Pn
Operation: 1 = output
0 = input
Notes:
If Fan Mode is selected, that is, the FAN bit of
the DEV_CFG register is set to one, P[7:4] are
automatically configured as open-drain out-
puts. They are then referred to as /FS[2:0] and
/SHDN. The DIR register has no effect on
these I/O bits while in Fan Mode.
Power-On Default Value: 0000 0000
b
, 00
h
no interrupts pending
Command_byte addess: 0000 0011
b
, 03
h
Type:
8-bits, read only
Sn
Flag for Pn input-change event when Pn is
configured as an input; Sn is set when the
corresponding input changes state.
Operation: 1 = change occurred
0 = no change occurred
Notes:
If Fan Mode is selected, that is, the FAN bit of
the DEV_CFG register is set to one, P[7:4] are
automatically configured as open-drain out-
puts. They are then referred to as /FS[2:0] and
/SHDN. No interrupts of any kind are
generated by these pins while in Fan Mode.
All status bits are cleared after any read
operation is performed on STATUS.
Bit Name:
Function:
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